Unless otherwise indicated herein, approaches described in this section are not prior art to the claims listed below and are not admitted to be prior art by inclusion in this section.
With the evolution of advanced integrated-circuit (IC) fabrication technology, the number of components and complexity of circuitry disposed on a chip have been increasing over time. Moreover, in applications such as portable devices (e.g., smartphones), consumer needs and market trend demand more and more functionalities, features and capabilities to be packed in one platform. Accordingly, solutions such as system-on-chip (SoC) and multi-core processors have gained popularity. Such a solution or platform typically includes a power management integrated circuit (PMIC) and a multi-core processor (e.g., application processor or central processing unit (CPU)), with the PMIC providing functions such as battery management, voltage regulation, and charging so as to power the multi-core processor for the multi-core processor to perform various operations.
FIG. 9 illustrates a conventional structure 900 for powering a multi-core processor 930, which is coupled to receive power from a PMIC 910 via a power delivery network 920. The power delivery network 920 includes a first ground plane 922, a second ground plane 924, and a power plane 926 between first and second ground planes 922 and 924. The first and second ground planes 922 and 924 as well as the power plane 926 are disposed in different layers of a printed circuit board (PCB). The power plane 926 is coupled between a power output terminal 912 of PMIC 910 and a power input terminal 932 of multi-core processor 930. The second ground plane 924 is coupled between a first ground terminal 914 of PMIC 910 and a second ground terminal 934 of multi-core processor 930. The power delivery network 920 also includes a pair of differential feedback lines 925A and 925B, with feedback line 925A coupled between a positive feedback terminal (FB+) 916 of PMIC 910 and the power plane 926 and feedback line 925B coupled between a negative feedback terminal (FB−) 918 of PMIC 910 and the second ground plane 924. Differential feedback lines 925A and 925B are used for differential voltage sensing to compensate IR drop between PMIC 910 and multi-core processor 930. The power delivery network 920 includes the PCB and the packages for PMIC 910 and multi-core processor 930. The capacitance of one or more decoupling capacitors (de-caps) is typically from 0.1 μF to 47 μF in the PCB and 0.1 μF in the package. Conventional surface-mount 47 μF capacitors are of 0805 (chip code) with dimensions of 2.0 mm (L)×1.25 mm (W)×1.25 mm (H). The larger the chip code is, the larger the dimension and more expensive, which is harmful to implement in portable devices with lower cost and smaller form factor.
FIG. 10 illustrates a simulation result 1000 of fluctuations in current and voltage with the conventional power delivery network 900 for multi-core processor 930 using a single-sided component placement (SSCP) configuration (depicted in FIG. 7). Referring to FIG. 10, as some or all of the cores of multi-core processor 930 are started up, whether one at a time in sequence or together simultaneously, there are resultant fluctuations and up to 16% voltage droop, as measured from a steady-state voltage level (e.g., 1 V), in the current drawn by the cores as well as in the voltage received by the cores even though some large size and expensive 47 μF de-caps are used in the PCB. This phenomenon tends to negatively impact the performance of multi-core processor 930 due to violation of the specification limit of 12% voltage droop. As any fluctuation in the power provided to multi-core processor 930 is passively sensed through differential feedback lines 925A and 925B, accuracy in the sensed fluctuation in the power provided to multi-core processor 930 tends to be less than ideal. Moreover, due to the passive nature in sensing fluctuations in the power provided to multi-core processor 930, an undesirable voltage droop in the power provided to multi-core processor 930 tends to occur when one or more cores of multi-core processor 930 are started up, as shown in FIG. 10.